1. Technical Field
The present invention relates to a semiconductor integrated circuit, and more particularly, to a delay locked loop (DLL) circuit provided in a semiconductor integrated circuit.
2. Related Art
In general, a DLL circuit provided in a semiconductor integrated circuit is used for providing an internal clock signal which leads the phase of a reference clock signal for a predetermined time. The reference clock signal being obtained by converting an external clock signal. As the internal clock signal utilized in the semiconductor integrated circuit is delayed through a clock buffer and a transfer line, a phase difference occurs between the internal clock signal and the external clock signal. Accordingly, the DLL circuit is used to solve such a problem that an output data access time increases. The DLL circuit performs such a control function that the internal clock signal leads the phase of the external clock signal for a predetermined time, in order to increase a valid data output interval.
FIG. 1 is a block diagram of a conventional DLL circuit.
Referring to FIG. 1, the DLL circuit includes: a clock input buffer 1 configured to buffer an external clock signal CLK_EXT to generate a reference clock signal CLK_REF; a delay line 2 configured to delay the reference clock signal CLK_REF in response to a delay control signal DLC and generate a delayed clock signal CLK_DLY; a clock driver 3 configured to drive the delayed clock signal CLK_DLY to generate an internal clock signal CLK_INT; a delay compensation unit 4 configured to delay the delayed clock signal CLK_DLY with a delay value obtained by modeling a delay value by delay elements provided on an output path of the delayed clock signal CLK_DLY, and generate a feedback clock signal CLK_FB; a phase detection unit 5 configured to compare the phase of the feedback clock signal CLK_FB with that of the reference clock signal CLK_REF to generate a phase detection signal PHD; an update control apparatus 6 configured to determine consecutive logic values of the phase detection signal PHD in response to the reference clock signal CLK_REF, and generate a valid interval signal VIT and an update control signal UDC; and a shift register 7 configured to update the logic value of the delay control signal DLC in response to the update control signal UDC when the valid interval signal VIT is enabled.
When the phase detection signal PHD is directly transferred to the shift register 7, the logic value of the phase detection signal PHD may change at a too short period. In this case, when the delay line 2 updates a delay amount, a malfunction may occur. To prevent such a malfunction, the update control apparatus 6 is provided to update a delay value which the shift register imparts to the delay line after the values of the phase comparison detection result are accumulated to a predetermined value.
In general, the update control apparatus 6 is implemented as a low-pass filter. That is, when the phase detection signal PHD consecutively maintains the same value for preset times, the update control apparatus 6 determines the logic value of the update control signal UDC in response to that. In general, however, the update control apparatus 6 determines the logic value of the phase detection signal PHD in response to a sample clock signal having the same frequency as the reference clock signal CLK_REF. Such an operation may significantly reduce the time for which the update control is apparatus 6 determines the logic value of the phase detection signal PHD. In such a state that the logic value determination time for the phase detection signal PHD is short, it is not easy to remove a high-frequency jitter of the phase detection signal PHD. Therefore, the reliability of the update control signal UDC inevitably decreases.
As such, the update control apparatus of the conventional DLL circuit does not have a configuration which stably performs an update operation to improve the stability of the DLL circuit.